Article by Ayman Alheraki on January 11 2026 10:37 AM
This table lists core legacy x86-64 assembly instructions with their machine code and encoding details.
| Mnemonic | Opcode | Encoding | Operands | ModR/M | SIB | Description |
|---|---|---|---|---|---|---|
| MOV | 89 /r | Legacy | reg, reg/mem | Yes | Optional | Move data between registers or memory |
| ADD | 01 /r | Legacy | reg, reg/mem | Yes | Optional | Add two operands |
| SUB | 29 /r | Legacy | reg, reg/mem | Yes | Optional | Subtract source from destination |
| MUL | F7 /4 | Legacy | reg/mem | Yes | Optional | Unsigned multiply (EAX * operand) |
| DIV | F7 /6 | Legacy | reg/mem | Yes | Optional | Unsigned divide (EDX:EAX / operand) |
| INC | FF /0 | Legacy | reg/mem | Yes | Optional | Increment operand by 1 |
| DEC | FF /1 | Legacy | reg/mem | Yes | Optional | Decrement operand by 1 |
| PUSH | 50+rd / FF /6 | Legacy | reg / reg/mem | Yes | Optional | Push value onto stack |
| POP | 58+rd / 8F /0 | Legacy | reg / reg/mem | Yes | Optional | Pop value from stack |
| CMP | 39 /r | Legacy | reg, reg/mem | Yes | Optional | Compare two operands |
This table lists key SIMD instructions using various vector extensions in x86-64, from SSE to AVX-512.
| Mnemonic | Opcode | Encoding | Operands | ISA Set | Description |
|---|---|---|---|---|---|
| ADDPS | 0F 58 /r | Legacy | xmm, xmm/m128 | SSE | Add packed single-precision floating-point values |
| ADDPD | 66 0F 58 /r | Legacy | xmm, xmm/m128 | SSE2 | Add packed double-precision floating-point values |
| VADDPS | C5 F8 58 /r | VEX | ymm, ymm, ymm/m256 | AVX | Add packed single-precision floats (256-bit) |
| VADDPD | C5 F9 58 /r | VEX | ymm, ymm, ymm/m256 | AVX | Add packed double-precision floats (256-bit) |
| VPADDQ | 66 0F D4 /r | VEX | xmm, xmm, xmm/m128 | AVX2 | Add packed quadword integers |
| VMULPS | C5 F8 59 /r | VEX | ymm, ymm, ymm/m256 | AVX | Multiply packed single-precision floats |
| VFMADD231PS | C4 E2 7D B8 /r | VEX | ymm, ymm, ymm/m256 | FMA3 | Fused multiply-add packed single-precision floats |
| VBROADCASTSS | C4 E2 7D 18 /r | VEX | ymm, m32 | AVX2 | Broadcast one float across ymm |
| VZEROALL | C5 F8 77 | VEX | — | AVX | Zero all YMM registers |
| VANDPS | C5 F4 54 /r | VEX | ymm, ymm, ymm/m256 | AVX | Bitwise AND of packed floats |
This table includes instructions used for AI workloads such as vector dot products, BF16 conversion, and AMX tile operations.
| Mnemonic | Opcode | Encoding | Operands | ISA Set | Description |
|---|---|---|---|---|---|
| VPDPBUSD | 62 F2 ED 48 50 /r | EVEX | zmm, zmm, zmm/m512 | AVX-512 VNNI | Multiply groups of unsigned/signed bytes and accumulate into dwords |
| VPDPBUSDS | 62 F2 ED 48 51 /r | EVEX | zmm, zmm, zmm/m512 | AVX-512 VNNI | Multiply-add with saturation |
| VPDPWSSD | 62 F2 ED 48 52 /r | EVEX | zmm, zmm, zmm/m512 | AVX-512 VNNI | Multiply signed word integers and accumulate |
| VPDPWSSDS | 62 F2 ED 48 53 /r | EVEX | zmm, zmm, zmm/m512 | AVX-512 VNNI | Multiply signed word integers with saturation and accumulate |
| VP4DPWSSDS | 62 F2 ED 48 54 /r | EVEX | zmm, zmm, zmm/m512 | AVX-512 VNNI | 4-dot-product with saturation |
| TILELOADD | C4 E2 7B 49 | AMX | tmm, mem | AMX | Load tile configuration from memory |
| TDPBSSD | C4 E2 7B 5A | AMX | tmm, tmm, tmm | AMX | Tile dot-product of signed bytes and signed bytes into dwords |
| VCVTNE2PS2BF16 | 62 F2 7D 48 72 /r | EVEX | zmm, zmm, zmm/m512 | AVX-512 BF16 | Convert packed single-precision to BF16 with rounding |
| VCVTNEPS2BF16 | 62 F2 7D 48 72 /r | EVEX | ymm, zmm/m512 | AVX-512 BF16 | Convert packed single-precision to BF16 |
| VCVTPH2PS | 62 F1 7D 48 13 /r | EVEX | zmm, ymm/m256 {1to16} | AVX-512 FP16 | Convert half-precision to single-precision |