Article by Ayman Alheraki on January 11 2026 10:37 AM
General-Purpose Registers
Special-Purpose Registers
Condition Flags
Instruction Formats
Instruction Encoding with Hexadecimal Examples
MIPS architecture features 32 general-purpose 32-bit registers, each serving specific conventions:skills.microchip.com+5Imperial College London+5Wikipedia+5
| Register | Name | Usage |
|---|---|---|
| $0 | zero | Constant zero |
| $1 | at | Assembler temporary |
| $2–$3 | v0–v1 | Function return values |
| $4–$7 | a0–a3 | Function arguments |
| $8–$15 | t0–t7 | Temporary registers |
| $16–$23 | s0–s7 | Saved registers |
| $24–$25 | t8–t9 | Temporary registers |
| $26–$27 | k0–k1 | Reserved for OS kernel |
| $28 | gp | Global pointer |
| $29 | sp | Stack pointer |
| $30 | fp | Frame pointer |
| $31 | ra | Return address |
Note: Register $0 is hardwired to zero and cannot be modified. Imperial College London+1Wikipedia+1
| Register | Description |
|---|---|
| HI | Stores the high-order 32 bits of multiplication/division results |
| LO | Stores the low-order 32 bits of multiplication/division results |
| PC | Program Counter, holds the address of the next instruction |
| EPC | Exception Program Counter, stores the address to return to after an exception |
| Status | Contains flags indicating the processor's state |
Unlike some architectures, MIPS does not have a dedicated condition flags register. Instead, conditional operations are performed using instructions that set registers based on comparisons. For example:
Set on Less Than (slt): Sets a register to 1 if one register is less than another; otherwise, sets it to 0.
slt $t0, $s1, $s2 # if $s1 < $s2, $t0 = 1; else $t0 = 0
Branch if Equal (beq) and Branch if Not Equal (bne): Used for conditional branching based on register comparisons.
xxxxxxxxxx beq $t0, $t1, label # if $t0 == $t1, branch to label bne $t0, $t1, label # if $t0 != $t1, branch to label
Note: Floating-point comparisons utilize the Floating Point Condition Codes (FCC) within the Floating Point Control Register (FCSR).
MIPS instructions are 32 bits wide and follow three primary formats:
Used for arithmetic and logical operations.
| Field | Bits | Description |
|---|---|---|
| opcode | 6 | Operation code (always 0 for R-type) |
| rs | 5 | Source register 1 |
| rt | 5 | Source register 2 |
| rd | 5 | Destination register |
| shamt | 5 | Shift amount (used in shift instructions) |
| funct | 6 | Function code specifying the exact operation |
Used for operations with immediate values and memory access.
| Field | Bits | Description |
|---|---|---|
| opcode | 6 | Operation code |
| rs | 5 | Source register |
| rt | 5 | Destination register |
| imm | 16 | Immediate value or address offset |
Used for jump instructions.
| Field | Bits | Description |
|---|---|---|
| opcode | 6 | Operation code |
| address | 26 | Target address |
Below are examples of MIPS instructions along with their binary and hexadecimal representations:
Description: Adds the contents of registers $t1 and $t2, stores the result in $t0.Users CS Utah
Binary Encoding:
xxxxxxxxxx opcode (6 bits): 000000 rs (5 bits): 01001 ($t1) rt (5 bits): 01010 ($t2) rd (5 bits): 01000 ($t0) shamt (5 bits): 00000 funct (6 bits): 100000 (add)
Hexadecimal: 0x012A4020
Description: Loads a word from memory address obtained by adding 32 to the contents of $s3 into $t0.
Binary Encoding:
xxxxxxxxxx opcode (6 bits): 100011 (lw) rs (5 bits): 10011 ($s3) rt (5 bits): 01000 ($t0) imm (16 bits): 0000000000100000 (32)
Hexadecimal: 0x8E680020
Description: Jumps to the address 0x00400000.
Binary Encoding:
xxxxxxxxxx opcode (6 bits): 000010 (j) address (26 bits): 00000000010000000000000000
Hexadecimal: 0x08010000
MIPS architecture includes support for SIMD (Single Instruction, Multiple Data) operations through extensions like MIPS DSP and MIPS SIMD Architecture (MSA). These extensions introduce additional instructions and registers to handle parallel data processing, beneficial in AI and multimedia applications.
For instance, MSA provides 128-bit vector registers and instructions for operations like vector addition, subtraction, and multiplication.
Note: The availability and specifics of these extensions depend on the MIPS processor variant in use.