Article by Ayman Alheraki on January 11 2026 10:37 AM
The ARMv9.2-A architecture, which the Apple M4 adheres to, defines 31 general-purpose 64-bit registers, named X0 through X30. Each can also be accessed as 32-bit W0–W30. Register X31 serves as the zero register (when used as a source) or the stack pointer (SP) (when used as a destination).
| Register | 64-bit Name | 32-bit Name | Description |
|---|---|---|---|
| X0–X7 | X0–X7 | W0–W7 | Function arguments / return values |
| X8 | X8 | W8 | Indirect result location register |
| X9–X15 | X9–X15 | W9–W15 | Temporary registers |
| X16–X17 | X16–X17 | W16–W17 | Intra-procedure-call scratch registers |
| X18 | X18 | W18 | Platform register (reserved) |
| X19–X28 | X19–X28 | W19–W28 | Callee-saved registers |
| X29 | FP | W29 | Frame pointer |
| X30 | LR | W30 | Link register (return address) |
| X31 | SP or ZR | WSP or WZR | Stack pointer or zero register |
The PSTATE register holds condition flags that reflect the outcomes of operations. These flags are:Reddit
| Flag | Bit Position | Description |
|---|---|---|
| N | 31 | Negative: Set if the result is negative |
| Z | 30 | Zero: Set if the result is zero |
| C | 29 | Carry: Set if there's a carry out |
| V | 28 | Overflow: Set if there's an overflow |
These flags are updated by instructions that have an 'S' suffix, such as ADDS or SUBS.
ARMv9-A instructions are uniformly 32 bits (4 bytes) in length and are encoded in little-endian format. Below are examples of common instructions with their hexadecimal representations:
| Instruction | Description | Hex Encoding |
|---|---|---|
MOV X0, #1 | Move immediate value 1 into X0 | 0xD2800020 |
ADD X1, X2, X3 | Add X2 and X3, store result in X1 | 0x8B030041 |
SUB X4, X5, #10 | Subtract immediate 10 from X5, store in X4 | 0xD1001454 |
| Instruction | Description | Hex Encoding |
|---|---|---|
AND X6, X7, X8 | Bitwise AND of X7 and X8, result in X6 | 0x8A0800E6 |
ORR X9, X10, X11 | Bitwise OR of X10 and X11, result in X9 | 0xAA0B0149 |
EOR X12, X13, X14 | Bitwise XOR of X13 and X14, result in X12 | 0xCA0E01AC |
| Instruction | Description | Hex Encoding |
|---|---|---|
B label | Unconditional branch to label | 0x14000000 |
BL label | Branch with link (call function) | 0x94000000 |
CBZ X0, label | Compare X0 with zero, branch if zero | 0xB4000000 |
Note: The actual hexadecimal encoding for branch instructions depends on the offset to the label.
The Apple M4 chip features a significantly enhanced Neural Engine, capable of performing up to 38 trillion operations per second, which is more than double the performance of its predecessor, the M3. This Neural Engine accelerates machine learning tasks, enabling faster on-device AI processing.Apple+2iMore+2Wikipedia+2
Additionally, the M4 supports the Scalable Matrix Extension (SME), which enhances matrix computations crucial for AI workloads. However, it does not support the Scalable Vector Extension (SVE). Wikipedia