MIPS architecture

• General-Purpose Registers

• Special-Purpose Registers

• Condition Flags

• Instruction Formats

• Instruction Encoding with Hexadecimal Examples

General-Purpose Registers (GPRs)

MIPS architecture features 32 general-purpose 32-bit registers, each serving specific conventions:skills.microchip.com+5Imperial College London+5Wikipedia+5

Note: Register $0 is hardwired to zero and cannot be modified. Imperial College London+1Wikipedia+1

Special-Purpose Registers

Condition Flags

Unlike some architectures, MIPS does not have a dedicated condition flags register. Instead, conditional operations are performed using instructions that set registers based on comparisons. For example:

• Set on Less Than (slt): Sets a register to 1 if one register is less than another; otherwise, sets it to 0.

  slt $t0, $s1, $s2  # if $s1 < $s2, $t0 = 1; else $t0 = 0

• Branch if Equal (beq) and Branch if Not Equal (bne): Used for conditional branching based on register comparisons.

  beq $t0, $t1, label  # if $t0 == $t1, branch to label
  bne $t0, $t1, label  # if $t0 != $t1, branch to label

Note: Floating-point comparisons utilize the Floating Point Condition Codes (FCC) within the Floating Point Control Register (FCSR).

Instruction Formats

MIPS instructions are 32 bits wide and follow three primary formats:

R-Type (Register)

Used for arithmetic and logical operations.

I-Type (Immediate)

Used for operations with immediate values and memory access.

J-Type (Jump)

Used for jump instructions.

Instruction Encoding with Hexadecimal Examples

Below are examples of MIPS instructions along with their binary and hexadecimal representations:

Example 1: add $t0, $t1, $t2

• Description: Adds the contents of registers $t1 and $t2, stores the result in $t0.Users CS Utah

• Binary Encoding:

  opcode (6 bits): 000000
  rs     (5 bits): 01001 ($t1)
  rt     (5 bits): 01010 ($t2)
  rd     (5 bits): 01000 ($t0)
  shamt  (5 bits): 00000
  funct  (6 bits): 100000 (add)

• Hexadecimal: 0x012A4020

Example 2: lw $t0, 32($s3)

• Description: Loads a word from memory address obtained by adding 32 to the contents of $s3 into $t0.

• Binary Encoding:

  opcode (6 bits): 100011 (lw)
  rs     (5 bits): 10011 ($s3)
  rt     (5 bits): 01000 ($t0)
  imm    (16 bits): 0000000000100000 (32)

• Hexadecimal: 0x8E680020

Example 3: j 0x00400000

• Description: Jumps to the address 0x00400000.

• Binary Encoding:

  opcode (6 bits): 000010 (j)
  address (26 bits): 00000000010000000000000000

• Hexadecimal: 0x08010000

AI and SIMD Extensions

MIPS architecture includes support for SIMD (Single Instruction, Multiple Data) operations through extensions like MIPS DSP and MIPS SIMD Architecture (MSA). These extensions introduce additional instructions and registers to handle parallel data processing, beneficial in AI and multimedia applications.

For instance, MSA provides 128-bit vector registers and instructions for operations like vector addition, subtraction, and multiplication.

Note: The availability and specifics of these extensions depend on the MIPS processor variant in use.