x86-64 Machine Code Encoding Real encoding examples with byte breakdowns

x86-64 Machine Code Encoding: Real encoding examples with byte breakdowns

This section presents practical, real-world examples of x86-64 machine code instruction encodings with detailed byte-level breakdowns. Understanding how instructions translate into machine code byte sequences is essential when designing an assembler. Each example demonstrates how prefixes, opcode bytes, ModR/M, SIB, displacement, and immediate fields combine to form the final binary encoding.

5.1 MOV Instruction Encoding Examples

Example 1: MOV RAX, RBX

Assembly:

mov rax, rbx

Explanation:

• 64-bit register-to-register move

• Requires REX prefix for 64-bit operand size

• Opcode 0x89 with ModR/M byte encoding destination and source registers

Byte Breakdown:

Final encoding: 48 89 D8

Example 2: MOV RAX, [RBP-0x10]

Assembly:

mov rax, [rbp-0x10]

Explanation:

• Memory to register move

• 64-bit operand with REX prefix

• ModR/M indicates 8-bit displacement with base register RBP

Byte Breakdown:

Final encoding: 48 8B 45 F0

Example 3: MOV RDX, 0x12345678

Assembly:

mov rdx, 0x12345678

Explanation:

• Move immediate 32-bit value to 64-bit register RDX

• Uses REX prefix with 64-bit operand

• Opcode 0xBA for MOV r64, imm32 (B8 + reg, reg=2 for RDX)

Byte Breakdown:

Final encoding: 48 BA 78 56 34 12 00 00 00 00

5.2 ADD Instruction Encoding Examples

Example 1: ADD RAX, RCX

Assembly:

add rax, rcx

Explanation:

• Register-to-register 64-bit addition

• Opcode 0x01 for ADD r/m64, r64

• Requires REX prefix

Byte Breakdown:

Final encoding: 48 01 C8

Example 2: ADD RDX, 5

Assembly:

add rdx, 5

Explanation:

• Immediate 8-bit addition to RDX

• Opcode 0x83 with opcode extension in ModR/M Reg field

• ModR/M specifies ADD operation

Byte Breakdown:

Final encoding: 48 83 C2 05

5.3 JMP Instruction Encoding Examples

Example 1: JMP +0x10

Assembly:

jmp 0x10

Explanation:

• Near relative jump with 4-byte displacement

• Opcode 0xE9 followed by signed 32-bit offset

Byte Breakdown:

Final encoding: E9 10 00 00 00

Example 2: JMP +0x7

Assembly:

jmp short 0x7

Explanation:

• Short relative jump (1-byte displacement)

• Opcode 0xEB followed by 1-byte offset

Byte Breakdown:

Final encoding: EB 07

5.4 CALL Instruction Encoding Examples

Example 1: CALL +0x20

Assembly:

call 0x20

Explanation:

• Near relative call with 4-byte displacement

• Opcode 0xE8 followed by 4-byte signed offset

Byte Breakdown:

Final encoding: E8 20 00 00 00

Example 2: CALL RAX

Assembly:

call rax

Explanation:

• Indirect call via register

• Opcode 0xFF with ModR/M specifying call opcode extension and register

Byte Breakdown:

Final encoding: FF D0

5.5 Summary and Insights

• REX Prefix is mandatory for 64-bit operand instructions and extended registers. Its bits control operand size (W), register extensions (R, X, B).

• Opcode bytes differ based on operand types, and some instructions use opcode extensions encoded in the ModR/M Reg field.

• ModR/M byte defines addressing modes, register operands, or memory indirect addressing modes.

• SIB bytes, when present, further define scaled indexed addressing, but are not required in these simple examples.

• Displacement and immediate values are encoded in little-endian format.

• Relative jumps and calls encode offsets relative to the next instruction, requiring assembler calculation during assembly.

Conclusion

These real encoding examples with byte breakdowns illustrate the precise binary layout of common instructions, a vital foundation for building an x86-64 assembler. Mastery of these details ensures accurate encoding and decoding of machine instructions, enabling robust assembler functionality.